Data processing systems, such as a microcomputer integrated circuit, are used with a wide range of peripheral devices, for example memory integrated circuits and application specific integrated circuits (ASICs). After an external bus access to a peripheral, some peripheral devices respond quickly and discontinue driving the external bus before the next bus cycle begins. Other peripheral devices respond more slowly and may not discontinue driving the external bus before the next bus cycle begins.
For example, if a slow peripheral device is driving the external bus of a data processing system during a first bus cycle, the slow peripheral device may continue to drive the external bus past the end of the first bus cycle and on into the beginning of the next or second bus cycle. Bus contention may result if both the data processing system and the slow peripheral device try to drive the external bus with different values during the beginning of the second bus cycle. Bus contention is especially a problem for data processing systems that use slow peripheral devices with multiplexed address and data bus configurations. However, bus contention may also be a problem for data processing systems that use non-multiplexed busses.
FIG. 5 illustrates an example of how a slow peripheral device may cause bus contention on a multiplexed address/data bus. In FIG. 5, the slow peripheral device continues to drive the first data value on the address/data bus long after the data strobe signal has been negated. Thus the data processing system may start driving the address value for the next bus cycle (i.e. the second address value) on the address/data bus while the slow peripheral device is still driving the first data value. Bus contention may also occur on split transaction busses or pipelined busses when the responses of multiple peripheral devices overlap.
Some existing data processing systems have addressed the problem of bus contention by inserting a fixed number of idle clocks after every access to each peripheral device. Unfortunately, however, this approach wastes a significant amount of time when both slow and fast peripheral devices must be accesses by a data processing system. The slow peripheral devices require the inserted idle clocks in order to prevent bus contention. However, the fast peripheral devices are able to stop driving the external bus quickly enough and thus do not need the inserted idle clocks. Thus the idle clocks inserted after accesses to fast peripheral devices are not necessary and waste valuable bus time.